1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. More specifically, it relates to a nonvolatile semiconductor memory, a data write-in method for the nonvolatile semiconductor memory and a memory card implementing the nonvolatile semiconductor memory, which suppress program disturbances arising due to an unselected high voltage being applied during a data write-in operation.
2. Description of the Related Art
According to a conventional data write-in method for a NAND flash memory, a program loop for writing data is repeated with an arbitrary step width and is stopped when all bits are written. The arbitrary step width is, for example, approximately 0.2 V for a multi-valued logic nonvolatile semiconductor memory.
A semiconductor memory has been disclosed in Japanese Patent Application Laid-Open No. 2002-140899. The disclosed memory is capable of providing processing results in a short time and includes a detection circuit that not only detects whether all program verification results are acceptable, but also detects the number of high-speed failures. The semiconductor memory, according to Japanese Patent Application Laid-Open No. 2002-140899, detects whether or not memory cells enter a predetermined data retaining state. This detection is possible by passing a predetermined amount of fail current based on whether or not a write-in operation or an erase operation for each memory cell within a collectively processed unit is completed, detecting the total amount of current flowing through that collectively processed unit by an A/D converter, and finally finding the number of predetermined incomplete states developed by collective processing (Japanese Patent Application Laid-Open No. 2002-140899 (e.g., see FIG. 1)).
A multi-valued nonvolatile memory with a simple structure capable of carrying out a highly accurate and high-speed write-in operation has been disclosed in Japanese Patent Application Laid-Open No. 2002-216486 (e.g., see FIG. 9). The multi-valued nonvolatile memory has a simple structure in which each single memory cell is capable of storing at least two bits of data is capable of processing a highly accurate and high-speed write-in operation. This is achieved by gradually increasing the amount of unit write-in data for a multi-valued nonvolatile memory in an erase state from a minimum unit during the first write-in operation, determining write-in characteristics of the memory cell based on the amount of written data permitting a predetermined threshold voltage equal to or less than primary threshold voltages, and deciding the amount of unit write-in data based on the determination results (Japanese Patent Application Laid-Open No. 2002-216486 (e.g., see FIG. 9)).
According to a conventional data write-in method for a NAND flash memory, a write-in loop reaching an upper limit (hereafter, referred to as Loop—max) in a page, which includes a low write-in speed, isolated bit. A problem arises that a program disturbance frequently occurs due to an unselected voltage. In addition, since a write-in loop runs until data is written in all memory cell transistors, or until the Loop—max in a page, which includes several bits of low write-in speed memory cell transistors, a program disturbance frequently occurs due to an unselected voltage. Furthermore, there is a problem that a program disturbance frequently occurs in all pages of a nonvolatile semiconductor memory including a ‘column failure’ where ‘0’ is changed to ‘1’ along the bit line length.
In addition, even with a conventional NAND flash memory, setting an upper limit value for a write-in voltage and limiting the write-in voltage below that upper limit value suppresses the influence of a program disturbance, however, there is a problem that write-in yield is adversely affected.